HDL Express

Welcome to HDL Express, the personal webpages of Kirk Weedman

HDL stands for Hardware Description Language.

This website also contains information on various Verilog/FPGA tutorials, Alternative Energy projects, and the progress of a new CPU architecture that I'm designing.

I'm an electronic design engineer specializing in contract Verilog RTL FPGA design, functional verification, testbench creation, simulation and debug. I have a varied background in other disciplines too.

My resume: Download the PDF version here. Download Word format here

Availability for new FPGA design/debugging contract work - October 2018

TIP Algorithm - a new dynamic instruction scheduling algorithm

Nov, 2018: Current Status of the new Out of Order CPU Architecture based on the TIP algorithm

This new dynamic instruction scheduling algorithm is not like the typical OoO methods being used today and the goal is to improve OoO IPC. Most Modern Out of Order CPU's, either use the Tomasulo or Scoreboarding algorithm (or some variant) for dynamic instruction scheduling. The method used in this CPU is completely different and simpler although there are several very specific rules it follows. There is no CDB or multiple CDBs, but multiple FU's that can execute in parallel in the same clock cycle. There is no register renaming, as the method effectively has infinite renaming, and thus no physical register set, just the architectural registers. It appears that as IPC increases linearly, the logic for the this new algorithm grows fairly linear instead of exponentially like the Tomasulo algorithm. The goal of building a working CPU is to prove the method works and to vary design parameters to get maximum performance (IPC throughput) for a given microarchitecture. The design is highly parameterized to allow many variations in the design. The latest design is now written in System Verilog RTL.

4/27/2017 - Since this algorithm can be applied to most any ISA, I am switching from the ARMv7 ISA to the RISC-V (RV32IM). RISC-V will be simpler to implement and there is software tool support for it.

See CPU History for more information about the progress on this architecture

10/5/2018 - New update: Arch. Reg. Dep. Control logic moved inside the RS block in preparation for new branch control logic that may use multiple branch block input streams instead of a single one as shown here (i.e. the Fetch, Decode, Microcode input stream) to minimze the number of wasted instructions/clock cycles when a branch mis- prediction occurs.

11/5/2018 - New block diagram of new Out of Order Microarchitecture. RS is now done differently although the TIP Algorithm has not changed.

2. Debugging Load/Store instructions.

3. Working on Fetch/Multiple Branch per clock logic

4. Adding/debugging RISC-V CSR instructions

5. New L1 Instruction and Data Caches being tested.

6.New Reservation Station/Architecture since end of July - still using same TIP algorithm.

7. Various functional unit simulations going on - still need to complete branch prediction

 

 

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